1) Field of the Invention
This invention relates generally to the planarization of integrated circuit dielectric structures and more particularly to an improved process for the global planarization of dielectric layers using an etch stop layer and a reversed reduce sized mask.
2) Description of the Prior Art
A major challenge in semiconductor manufacturing is the planarization of insulating layers formed over depressions and raised portions over a semiconductor structure (e.g., a wafer). The depression in the surface of the semiconductor structure can be a space located between conductor tracks (for example of aluminum or of polycrystalline ) disposed on a substrate, but may also be a groove etched into the substrate or it may be a window provided in an insulating layer. Local planarization is the filling of small spaces (gaps) between raised portions while global planarization is the filling of wider spaces (gaps).
A typical structure would be formed in the following manner. A conductive layer would be patterned over a semiconductor structure (or a trench formed in a wafer). The conductor is often covered with a protection layer, such as a low temperature oxide like a plasma enhanced oxide. An insulating layer would be formed over the irregular surface. The insulating layer would be planarized.
There are numerous known methods for planarizing wafer during fabrication of integrated circuits, for example, block resist and resist etch back, block resist and spin on glass. For example, the raised portions (hills of conductor or substrate) can be covered with an insulating layer such as a spin on glass. To planarized the hills and valleys, the spin-on glass is etched back to attempt to achieve a smooth surface on the integrated circuit. However, as the spin-on-glass is etched through in the region over the raised portions (e.g., exposed an underlying oxide layer), oxygen free radicals are released from the plasma enhanced oxide which enhances the etch rate of the spin-on-glass in the valley regions. The etch rate of the spin-on-glass can be 50% or higher than that of the plasma-enhanced oxide, depending on the etch chemistry. Thus, the planarization of the integrated circuit involves critical process parameters that are difficult to control, especially when an etch into the underlying plasma-enhance oxide is required.
Also chemical-mechanical polish (CMP) has been used in planarization. chemical-mechanical polishing (CMP) provides full wafer planarization without additional masking or coating steps. However, one of the difficulties encountered with CMP for hollow/valley/trench planarization is the "dishing" effect which occurs in wide low spots (e.g., valleys between interconnects or metal lines or trenches) (i.e., usually &gt;25 .mu.m). Dishing is the removal portions of insulating layer in "open areas" below the plane of the insulating layer over level or higher area. Dishing is particularly sever in hollows wider than 100 .mu.m. The "dishing" effect during polishing results in thinning of the dielectric in wide trenches resulting in a nonplanar surface. The polish rate is affected by the topology of the surrounding areas.
Much effort has been directed to modify the planarization etch back and polish processes, equipment, and materials in an attempt to improve the planarization process. For example, U.S. Pat. No. 5,015,602 (Van Der Plas et al.) shows a method of planarizing an oxide layer covering trenches using a reverse trench mask. U.S. Pat. No. 5,350,486 (Huang) shows a method of planarizing a glass layer over metal lines. The patent uses a reverse metal mask to etch the glass layer. U.S. Pat. No. 5.518,950 (Ibok et al.) shows another negative resist pattern planarization. However, these methods can be further improved upon by providing a simpler, more manufacturable process which yields a more planar surface.